1. Field of Invention
This invention relates to integrated circuit packaging, and more particularly, to a packaging layout that provides high density routing of signal lines among a pair of signal conductor planes embedded between power and ground conductor planes.
2. Description of Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
During manufacture of an integrated circuit (e.g., a microprocessor), signal lines formed upon the silicon substrate, which are to be connected to external devices, may be formed such that these lines terminate at flat metal contact regions called input/output (I/O) pads. Following manufacture, the integrated circuit may typically be secured within a protective semiconductor device package. Each I/O pad of the integrated circuit may be connected to one or more terminals of the device package. The terminals of a device package are typically arranged about the periphery of the package. Fine metal wires may be used to connect the I/O pads of the chip to terminals of the device package. Some types of device packages have terminals called xe2x80x9cpinsxe2x80x9d for insertion into holes in a printed circuit board (PCB). Other types of device packages have terminals called xe2x80x9cleadsxe2x80x9d for attachment to flat metal contact regions on an exposed surface of a PCB.
As integrated circuit fabrication technology improves, manufacturers are able to integrate more and more circuits onto single silicon substrates. As the number of circuits on a single chip increases, however, the number of signal lines which need to be connected to external devices also increases. The corresponding numbers of required I/O pads and device package terminals increase as well as the complexities and costs of the device packages. Constraints of high volume PCB assembly operations place lower limits on the physical dimensions of and distances between device package terminals. As a result, the areas of peripheral-terminal device packages having hundreds of terminals are largely proportional to the number of terminals. These larger packages with fine-pitch leads are subject to mechanical damage during handling or testing. For example, mishandling may result in a loss of lead coplanarity, thereby adversely affecting PCB assembly yields. In addition, the lengths of signal lines from chip I/O pads to device package terminals increase with the number of terminals, and the high-frequency electrical performance of larger peripheral-terminal device packages suffer as a result.
Unlike more conventional peripheral-terminal device packages, grid array semiconductor device packages have terminals arranged in a two-dimensional array across the underside surface of the device package. As a result, the physical dimensions of grid array device packages having hundreds of terminals are much smaller than their peripheral-terminal counterparts. Such smaller packages are highly desirable in portable device applications such as laptop and palmtop computers and hand-held communications devices such as cellular telephones. In addition, the lengths of signal lines from the chip I/O pads to device package terminals are shorter, thus the high-frequency electrical performances of grid array device packages are typically better than those of corresponding peripheral-terminal device packages. Grid array device packages also allow the continued use of existing PCB assembly equipment developed for peripheral-terminal devices.
An increasingly popular type of grid array device package is the ball grid array (BGA) device package. A BGA device package includes a chip mounted upon a larger substrate substantially made of, for example, fiberglass-epoxy printed circuit board material or a ceramic material (e.g., aluminum oxide, alumina (Al2O3), or aluminum nitride (AlN)). Many BGA device packages have die areas dimensioned to receive integrated circuit chips and use established wire bonding techniques to electrically connect the I/O pads of the chips to corresponding flat metal xe2x80x9cbonding fingersxe2x80x9d adjacent to the die areas. During wire bonding, the I/O pads of the chip may be electrically connected to corresponding bonding fingers by fine metal wires (i.e., bonding wires). The substrate may include one or more layers of signal lines (i.e., signal traces or interconnects) which may connect bonding fingers to corresponding members of a set of bonding pads arranged in a two-dimensional array across the underside surface of the device package. Members of the set of bonding pads are coated with solder and function as device package terminals. The resulting solder balls on the underside of the BGA device package allow the device to be surface mounted to an ordinary PCB. During PCB assembly, the solder balls are placed in physical contact with corresponding bonding pads of the PCB. The solder balls are then heated long enough for the solder to flow. When the solder cools, the bonding pads on the underside of the chip are electrically and mechanically coupled to the bonding pads of the PCB.
A BGA device package on a plastic carrier is known as a plastic ball grid array (PBGA) device. A conventional PBGA, may include, for example, four layers of copper metal conductors separated by three dielectric layers. Normally, the top copper metal layer includes signal traces, the second copper metal layer is the ground, the third copper metal layer is the power plane, and the bottom copper metal layer is the ball pad. A die is bonded to the top of this package. The die may be wirebonded to the substrate, which may be molded to cover and protect the die and the gold wire.
As dies become more dense and complex, the signal trace density of packages also increases. There are at least two problems associated with increases in trace density. First, the area on the signal trace conductor layer may be insufficient for the required signal traces. Second, increasing signal trace density on a package may lead to increased cross talk between the signals and overall noise of the package.
The problems outlined above may be in large part addressed by a package that includes a substrate having high density routing. According to one embodiment, a semiconductor substrate may include an upper surface upon which a bonding finger resides. The semiconductor substrate may also include a lower surface upon which a solder ball resides. In addition, the semiconductor substrate may include a signal conductor plane on which a signal trace conductor resides a dielectrically spaced distance between the upper surface and the lower surface. The semiconductor substrate may further include a first via extending perpendicular to the upper surface and the signal conductor plane as a unibody structure. The first via may connect the bonding finger to a first portion of the signal trace conductor. Furthermore, the semiconductor substrate may include a second via extending perpendicular to the lower surface and the signal conductor plane as a unibody structure. The second via may connect the solder ball to a second portion of the signal trace conductor extending along the signal conductor plane from the first portion coupled thereto.
In an embodiment, the first portion may be directly below the bonding finger, and the second portion may be directly above the solder ball. The signal conductor plane may extend dielectrically between a planar power conductor and a planar ground conductor. The planar power conductor may extend a distance substantially equal to a soldermask thickness beneath the upper surface.
In an embodiment, the first via may extend a spaced distance from an inner surface of an aperture created through a portion of the planar power conductor. In an additional embodiment, the second via may extend a spaced distance from an inner surface of an aperture created through a planar power conductor arranged across a lower surface of the substrate.
In an embodiment, a semiconductor substrate may include a set of first bonding fingers spaced across an upper surface of the substrate along a first line parallel to an area adapted to receive an integrated circuit. The semiconductor substrate may also include a set of second bonding fingers spaced across the upper surface along another line parallel to the first line and farther from the area adapted to receive the integrated circuit than the first bonding fingers. Further, the semiconductor substrate may also include a set of coplanar first signal trace conductors dielectrically spaced below the upper surface and extending from a first point vertically aligned with respective first bonding fingers to a second point closer to the area adapted to receive the integrated circuit than the first point. The semiconductor substrate may further include a set of co-planar second signal trace conductors dielectrically spaced above the first signal trace conductors and extending from a third point vertically aligned with respective the second bonding fingers to a fourth point farther from the area adapted to receive the integrated circuit than the third point.
In an embodiment, a first via may electrically couple a respective pair of one of the first bonding fingers to the first point. In addition, a second via may electrically couple the second point to one of a first set of solder balls arranged on a lower surface of the substrate. A third via may electrically couple a respective pair of one of the second bonding fingers to the third point. Furthermore, a fourth via may electrically couple the fourth point to one of a second set of solder balls arranged on a lower surface of the substrate. The first set of solder balls may be closer to the area adapted to receive the integrated circuit than the second set of solder balls.
According to an embodiment, an integrated circuit package may include a first signal conductor that may be dielectrically spaced between an upper surface on which an integrated circuit is placed and a lower surface on which first and second solder balls are placed. A first signal conductor may be adapted to carry an electrical signal for a bonded finger arranged within a first row of bonding fingers extending across the upper surface to the first solder ball. The integrated circuit package may also include a second signal conductor. The second signal conductor may be adapted to carry an electrical signal from a bonded finger arranged within a second row of bonding fingers parallel to the first row and extending across the upper surface to the second solder ball. The first row of bonding fingers and the first solder ball may be closer to the integrated circuit than the second row of bonding fingers and the second solder ball.
The first signal conductor may be arranged within the first signal conductor plane, and the second signal conductor may be arranged within the second signal conductor plane. A planar ground conductor may be dielectrically spaced between the first and second signal conductor planes. The upper surface may include a first planar power conductor that may be dielectrically spaced from the first and second rows of bonding fingers and the planar ground conductor. The second planar power conductor may be dielectrically spaced between the first signal conductor plane and the first and second solder balls. The second planar power conductor may be approximately 160 xcexcm from the first and second solder balls.
The integrated circuit package may include a single crystalline structure. The bonded fingers within the first and second rows of bonded fingers may be electrically connected to bonding pads on the integrated circuit by either wires or reflow solder. The integrated circuit package may also include an encapsulate that surrounds at least a portion of the integrated circuit and the upper surface.
There are several advantages to a semiconductor package that includes a semiconductor substrate as described in various embodiments herein. For example, a substrate, as described herein, may allow for high density routing of signal lines with a reduction of noise and cross talk. Cross talk is caused by signals from one signal line leaking over into another nearby conductor because of capacitance or inductive coupling or both. By separating the signals between two dielectrically separated signal planes, the mutual capacitance and inductance effects necessary for cross talk diminish. Further, the second signal conductor plane may be placed approximately 160 xcexcm from the solder balls for the purpose of making the overall substrate approximately 560 xcexcm thick. This thickness may cause the substrate to be less fragile and more easily handled during the manufacturing process, thereby facilitating manufacturing.